Browsing by Author "Kos, Andrzej Jan"

Now showing 1 - 3 of 3

Access status: Open Access ,
Asynchroniczne sterowanie aktywnością bloków funkcjonalnych systemów scalonych
(2006-11-23) (Data obrony: 2010) Mikuła, Sławomir
Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki
The paper studies the integrated circuit's thermal aspects, dynamic temperature changes on the surface of the chip and the management mechanisms of the operating systems in such a way as to minimize the maximum instantaneous temperature of the system without compromising computing power. The study was carried out covering the full cycle of research on the thermal analysis of a modular integrated circuit. Author developed a numerical method for calculating the temperature using the Green function. Based on the results of the thermal analysis author proposes an asynchronous control mechanism for activity of an integrated circuit's module. Next step was to develop mechanisms for choosing the optimal module of an integrated circuit who performed the computing task regarding thermal aspects of a whole integrated circuit. At this stage, the author undertook analysis of the thermal dynamics of an integrated circuit. It introduces a Point Heating Time variable, which was used to determine the dynamic conditions of the integrated circuit module regarding physical conditions. Based on experimental results author has developed a control algorithm of a multi-core system. The algorithm was implemented in the GNU/Linux operating system with the Cell processor as the target hardware platform. The work has been carried out so as to lead to a better use of the thermodynamic properties of semiconductor structures.
Access status: Open Access ,
Problem projektowania topografii systemów wielkiej skali integracji
(2005-01-20) (Data obrony: 2008) Nagórny, Zbigniew
Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki
The aim of this work is to solve the problem of wire length optimization in VLSI systems. In current VLSI systems, delays caused by circuit interconnections have a great impact on the functional properties of circuits. In this work, the method which utilizes the Hopfield network is chosen, for the possibility of hardware realization of this method. Hardware realization of the cell placement could significantly decrease computation time. In this work, a survey of cell placement techniques is presented. The modified Hopfield network cost function for the problem of minimization of the total wire length and auto-feedback of neurons in the Hopfield network are originally used. These modifications enabled a significant improvement on the quality of results obtained. The Hopfield network is originally used for the minimization of the total wire length in a circuit with fixed position pads. In this work, the Hopfield network for the minimization of the total wire length in a circuit with nets containing multiple terminals and also a method for the correction of the wire length estimation in the net are originally used. The Hopfield network was originally used as processing units in parallel placement, which enabled very efficient minimization of the wire length in VLSI circuits. The excellent results of using the Hopfield network for other optimization problems, for example of the travelling salesman problem are presented. The possibilities of the Hopfield network application for VLSI systems topography design are described.
Access status: Open Access ,
Reduction of energy losses in CMOS circuits considering die temperature
(2002-05-23) (Data obrony: 2008) Gołda, Adam
Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki
In this dissertation, the elaboration of predictive techniques used in dynamic power management has been presented. The supervisors that are dedicated to managing these predictive methods, which are based on DCT, DFS, and DVS techniques, have also been worked out. These techniques belong to rare methods of energy minimisation that take into account chip temperature. The author of this dissertation has analysed each component of energy consumption by means of theoretical investigations, simulations, and measurements. The temperature influence on each part of energy losses have also been taken into account. The considerations have been performed for wide range of technologies from 3 $\mu$m to 32 nm. The next stage is consideriation of thermal phenomena in solids and electro-thermal interactions. Using original software EThS and test chips designed by the author the electro-thermal models are matched and verified. The new predictive techniques that are based on common DCT, DFS, and DVS methods have been worked out. They are dedicated to high efficiency systems in order to keep theirs throughput on the possible maximum level. They consist in cooperation of supervisory unit with operating system that has to deliver data about the curreni and future process requirements of power consumption. The simply shape of equations, which describes the behaviour of theirs supervisors, allows dired implementation in neural networks. The presented supervisors can also be easily applied in the other hardware or software. Not only the supervisors turn a profit in energy consumption, they also gain in performance.