Browsing by Subject "FPGA"

Now showing 1 - 20 of 143

Access status: Open Access ,
2-DOF piezoelectric actuator controller based on FPGA
(2013) Prusak, Daniel; Karpiel, Grzegorz; Gac, Konrad
This article presents the method for controlling the piezolegs motor with the application of the FPGA (Field-programmable gate array) system and presents the results of conducted tests of the motor slider displacement, with various steering signal configurations. It includes also the review of piezoelectric motors solutions and characteristics of systems, based on FPGA systems. Suggested steering solution can be used for subsequent tests on piezolegs drives and can constitute positioning system element.
Access status: Open Access ,
A physical model of quantum bit behavior based on a programmable FPGA integrated circuit
(Wydawnictwa AGH, 2024) Długopolski, Jacek; Sadowski, Marcin; Suleja, Wawrzyniec
The rapidly developing field of quantum computing and the ongoing lack of widely available quantum computers create the need for scientists to build their simulators. However, mathematical simulation of such circuits usually ignores many aspects and problems found in real quantum systems. In this article, the authors describe a quantum bit emulator based on FPGA integrated circuits. In this case, FPGA technology provides real-time massive parallelism of the modeled physical phenomena. The modeled QUBIT is represented using a Bloch sphere. Its quantum state is set and modified only by precise pulses of an electrical signal, and with the help of similar pulses, it manifests its current state in real time. The constructed QUBIT was additionally equipped with decoherence mechanisms and with circuits that intentionally respond to internal and external noises that distort its current quantum state. This article presents and discusses how such a physically built emulator works.
Access status: Restricted ,
Abandoned luggage detection using FPGA integrated circuit
(Data obrony: 2016-09-28) Skirzyński, Artur
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
Access status: Restricted ,
Akceleracja sprzętowa głębokich konwolucyjnych sieci neuronowych dla potrzeb sytemu detekcji obiektów
(Data obrony: 2018-09-05) Przewłocka, Dominika
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
Access status: Restricted ,
Akceleracja sprzętowa głębokich sieci neuronowych do detekcji obiektów na podstawie danych z LiDAR z wykorzystaniem układów reprogramowalnych
(Data obrony: 2020-08-26) Stanisz, Joanna; Lis, Konrad
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
Access status: Restricted ,
Akceleracja sprzętowa głębokich sieci neuronowych do detekcji obiektów na podstawie danych z LiDAR z wykorzystaniem układów reprogramowalnych
(Data obrony: 2020-08-26) Lis, Konrad; Stanisz, Joanna
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
Access status: Open Access ,
Algorytm sterowizyjny wykorzystany do wyznaczenia orientacji palców dłoni i możliwości jego implementacji w układzie FPGA
(Wydawnictwa AGH, 2008) Zawadzki, Artur
In this dissertation was presented suggested by the author algorithm, which is used for appointment of orientation of hand fingers and is based on the stereovision algorithm. Results was presented for the model of hand and for the real hand. Structure of algorithm is well directed on using FPGA systems from the consideration of parallelly occurring operations. On that account it takes attempt of verification efficency of algorithm implementation with use of the Handel-C language in FPGA systems.
Access status: Restricted ,
Analiza możliwości wykorzystania narzędzia Vivado HLS w implementacji sprzętowej wbudowanych systemów wizyjnych
(Data obrony: 2018-10-16) Woźniak, Mateusz
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
Access status: Restricted ,
Aplikacja komputerowa do wspomagania projektowania procesorów dedykowanych.
(Data obrony: 2019-07-11) Duda, Filip
Wydział Informatyki, Elektroniki i Telekomunikacji
Access status: Restricted ,
Application of FPGA Xilinx tecvhnology to measurement of power quality coefficients
(Data obrony: 2016-10-12) Błaszkiewicz, Łukasz
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
Access status: Restricted ,
Badanie jakości sygnałów transmisji różnicowej za pomocą systemu pomiarowego PXI
(Data obrony: 2019-12-09) Niemiec, Jan
Wydział Informatyki, Elektroniki i Telekomunikacji
Access status: Open Access ,
Bezczujnikowy układ napędowy z bezszczotkowym silnikiem prądu stałego z magnesami trwałymi (BLPMDCM) sterowany sygnałem proporcjonalnym do modułu prądu źródła
(Data obrony: 2008-11-26) Siostrzonek, Tomasz
Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki
In the PhD thesis the results of research of drive system with Brushless Permanent Magnet DC Motor are shown. The current regulation of this machine can be worked out in the same way as for classic DC machine with separately excited, by means of PI controller. The feedback signal for PI controller is a signal, which is proportional to current wave (Id) of DC source. The permanent magnet machine is supplied by inverter which fulfils commutator. Rotor position information is required in order to determine the phase voltage switching points. The position information is provided by the three Hall effect sensors. First step in the development of a BLDC control without any position sensor is the detection and analysis of the motor back-EMF. The motor is fed two phase on, with 60° commutation periods, and detection of the commutation instant is performed by sensing the back-EMF in the non-fed phase. In drive system the current controller (PI) and speed controller (P) were implement. The drive system in the Flywheel Energy Storage System was used. Three phase rectifier is a part of Power Electronic system for supply of brushless DC motor. Additionally, bidirectional power flow (possibility of energy return from drive system to supply system) and DC voltage stabilization was possible.
Access status: Restricted ,
Biblioteka modułów sprzętowych do segmentacji obiektów pierwszoplanowych
(Data obrony: 2017-07-14) Janus, Piotr
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
Access status: Restricted ,
Budowa i weryfikacja opartego na układach FPGA generatora pakietów z kontrolą integralności danych
(Data obrony: 2019-10-24) Adamczyk, Konrad; Duda, Patryk
Wydział Informatyki, Elektroniki i Telekomunikacji
Access status: Restricted ,
Budowa i weryfikacja opartego na układach FPGA generatora pakietów z kontrolą integralności danych
(Data obrony: 2019-10-25) Duda, Patryk; Adamczyk, Konrad
Wydział Informatyki, Elektroniki i Telekomunikacji
Access status: Open Access ,
Compressing sentiment analysis CNN models for efficient hardware processing
(Wydawnictwa AGH, 2020) Wróbel, Krzysztof; Karwatowski, Michał; Wielgosz, Maciej; Pietroń, Marcin; Wiatr, Kazimierz
Convolutional neural networks (CNNs) were created for image classification tasks. Shortly after their creation, they were applied to other domains, including natural language processing (NLP). Nowadays, solutions based on artificial intelligence appear on mobile devices and embedded systems, which places constraints on memory and power consumption, among others. Due to CNN memory and computing requirements, it is necessary to compress them in order to be mapped to the hardware. This paper presents the results of the compression of efficient CNNs for sentiment analysis. The main steps involve pruning and quantization. The process of mapping the compressed network to an FPGA and the results of this implementation are described. The conducted simulations showed that the 5-bit width is enough to ensure no drop in accuracy when compared to the floating-point version of the network. Additionally, the memory footprint was significantly reduced (between 85 and 93% as compared to the original model).
Access status: Open Access ,
Computation acceleration on SGI RASC: FPGA based reconfigurable computing hardware
(Wydawnictwa AGH, 2008) Jamro, Ernest; Janiszewski, Marcin; Machaczek, Krzysztof; Russek, Paweł; Wiatr, Kazimierz; Wielgosz, Maciej
In this paper a novel method of computation using FPGA technology is presented. In several cases this method provides a calculations speedup with respcct to the General Purpose Processors (GPP). The main concept of this approach is based on such a design of computing hardware architecture to fit algorithm dataflow and best utilize well known computing techniques as pipelining and parallelism. Configurable hardware is used as a implementation platform for custom designed hardware. Paper will present implementation results of algorithms those are used in such areas as cryptography, data analysis and scientific computation. The other promising areas of new technology utilization will also be mentioned, bioinformatics for instance. Mentioned algorithms were designed, tested and implemented on SGI RASC platform. RASC module is a part of Cyfronet's SGI Altix 4700 SMP system. We will also present RASC modern architecture. In principle it consists of FPGA chips and very fast, 128-bit wide local memory. Design tools avaliable for designers will also be presented.
Access status: Restricted ,
Design of a hardware block for an FPGA chip for tasks in robotics
(Data obrony: 2021-02-25) Górzyński, Mateusz
Wydział Inżynierii Mechanicznej i Robotyki
Access status: Restricted ,
Detekcja obiektów z wykorzystaniem sieci neuronowych o zredukowanej precyzji obliczeń
(Data obrony: 2019-01-28) Kaczmarski, Piotr
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
Access status: Restricted ,
Detekcja obiektu o kulistym kształcie w układzie rekonfigurowalnym
(Data obrony: 2020-01-17) Wajda, Konrad
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej