Browsing by Subject "układ FPGA"

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Generator sygnałowy z bezpośrednią cyfrową syntezą oparty o układ FPGA
(Data obrony: 2021-01-18) Kwaśniewicz, Karol
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
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Implementacja prostego systemu mikroprocesorowego opartego o soft procesor.
(Data obrony: 2021-01-22) Twaróg, Mateusz
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
Access status: Open Access ,
Jednofazowy prostownik wielokomórkowy z sinusoidalnym prądem źródła
(Data obrony: 2008) Baszyński, Marcin
Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki
The multicell converters family and their topologies derive from the flying capacitor converters (capacitors clamped). Converters of this type are made from recurrent, identical modules (cells). The number of input voltage levels depend on the number of cells in the converter. A single cell of a two-leg AC/DC convertes consists of four switches with anti-parallel diodes and two capacitors. The input voltage uin of the three-cell converter has an ac component of $3f_{c}$ frequency ($f_{c}$ - single cell switching frequency). However, when $uc_{n} \neq (Nu_{CF})/3$ ($U_{CF}$- output capacitors voltage, $n$- number of cell), an additional component of $f_{c}$ frequency occurs in the output voltage. Existence of the unbalance component makes $f_{c}$ frequency current flow trough the balancing circuit $i_{b}$ and the cells' capacitors. In the PhD thesis the problems of a proper selection of the balancing circuit parameters, selection of the output and the internal capacitors parameter, influence of the converter to the AC source (power factor), influence of the voltage collapse to the voltage of the capacitors and FPGA-based modelling of the converter were discussed. This PhD dissertation presents the practical result of realization the multicell AC/DC converter with FPGA control.
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Podsystem obsługi wyświetlacza dotykowego LCD w układzie FPGA
(Data obrony: 2021-01-26) Bielecki, Łukasz
Wydział Informatyki, Elektroniki i Telekomunikacji
Access status: Open Access ,
Problem projektowania topografii systemów wielkiej skali integracji
(2005-01-20) (Data obrony: 2008) Nagórny, Zbigniew
Wydział Elektrotechniki, Automatyki, Informatyki i Elektroniki
The aim of this work is to solve the problem of wire length optimization in VLSI systems. In current VLSI systems, delays caused by circuit interconnections have a great impact on the functional properties of circuits. In this work, the method which utilizes the Hopfield network is chosen, for the possibility of hardware realization of this method. Hardware realization of the cell placement could significantly decrease computation time. In this work, a survey of cell placement techniques is presented. The modified Hopfield network cost function for the problem of minimization of the total wire length and auto-feedback of neurons in the Hopfield network are originally used. These modifications enabled a significant improvement on the quality of results obtained. The Hopfield network is originally used for the minimization of the total wire length in a circuit with fixed position pads. In this work, the Hopfield network for the minimization of the total wire length in a circuit with nets containing multiple terminals and also a method for the correction of the wire length estimation in the net are originally used. The Hopfield network was originally used as processing units in parallel placement, which enabled very efficient minimization of the wire length in VLSI circuits. The excellent results of using the Hopfield network for other optimization problems, for example of the travelling salesman problem are presented. The possibilities of the Hopfield network application for VLSI systems topography design are described.
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Sieci neuronowe w systemie pomiaru naprężeń z zastosowaniem FPGA
(Data obrony: 2020-12-02) Kokoszka, Krystian
Wydział Inżynierii Mechanicznej i Robotyki
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Wykorzystanie technologii FPGA do sterowania układów energoelektronicznych
(Data obrony: 2017-01-25) Mach, Fabian
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
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Zdalnie dostępna platforma dydaktyczna z układem FPGA
(Data obrony: 2020-09-29) Caputa, Wojciech
Wydział Informatyki, Elektroniki i Telekomunikacji