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Pietroń, Marcin

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informatyka techniczna i telekomunikacja
informatyka

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Now showing 1 - 7 of 7
  • Item type:Article, Access status: Open Access ,
    Compressing sentiment analysis CNN models for efficient hardware processing
    (Wydawnictwa AGH, 2020) Wróbel, Krzysztof; Karwatowski, Michał; Wielgosz, Maciej; Pietroń, Marcin; Wiatr, Kazimierz
    Convolutional neural networks (CNNs) were created for image classification tasks. Shortly after their creation, they were applied to other domains, including natural language processing (NLP). Nowadays, solutions based on artificial intelligence appear on mobile devices and embedded systems, which places constraints on memory and power consumption, among others. Due to CNN memory and computing requirements, it is necessary to compress them in order to be mapped to the hardware. This paper presents the results of the compression of efficient CNNs for sentiment analysis. The main steps involve pruning and quantization. The process of mapping the compressed network to an FPGA and the results of this implementation are described. The conducted simulations showed that the 5-bit width is enough to ensure no drop in accuracy when compared to the floating-point version of the network. Additionally, the memory footprint was significantly reduced (between 85 and 93% as compared to the original model).
  • Item type:Article, Access status: Open Access ,
    Prototyp systemu profilowania pętli kodu źródłowego jako narzędzia analizy kodu w celu efektywnego przyspieszenia obliczeń wielkiej skali
    (Wydawnictwa AGH, 2010) Pietroń, Marcin; Russek, Paweł; Wiatr, Kazimierz
    This paper presents the research on FPGA based acceleration of HPC applications. The most important step to achieve this goal is to extract code that can be sped up. A major drawback is the lack of a tool which could do it. The HPC applications usually consist of a huge amount of complex source code. This is one of the reasons why the process of acceleration should be as automated as possible. Another reason is to make use of HLL (High Level Languages) such as Mitrion-C and Impulse-C. Loop profiling is one of the steps to check if the insertion of HLL to existing HPC source code is possible to gain acceleration of these applications. Hence the most important step to achieve acceleration is to extract the most time consuming code and data dependency, which makes the code easier to be pipelined and parallelized. Data dependency also gives information on how to implement algorithms in an FPGA circuit with the minimal initialization of it during the execution of algorithms.
  • Item type:Article, Access status: Open Access ,
    Accelerating SELECT WHERE and SELECT JOIN queries on a GPU
    (Wydawnictwa AGH, 2013) Pietroń, Marcin; Russek, Paweł; Wiatr, Kazimierz
    This paper presents implementations of a few selected SQL operations using the CUDA programming framework on the GPU platform. Nowadays, the GPU’s parallel architectures give a high speed-up on certain problems. Therefore, the number of non-graphical problems that can be run and sped-up on the GPU still increases. Especially, there has been a lot of research in data mining on GPUs. In many cases it proves the advantage of offloading processing from the CPU to the GPU. At the beginning of our project we chose the set of SELECT WHERE and SELECT JOIN instructions as the most common operations used in databases. We parallelized these SQL operations using three main mechanisms in CUDA: thread group hierarchy, shared memories, and barrier synchronization. Our results show that the implemented highly parallel SELECT WHERE and SELECT JOIN operations on the GPU platform can be significantly faster than the sequential one in a database system run on the CPU.
  • Item type:Article, Access status: Open Access ,
    The ontology alignment system based on algorithms using data similarity metrics
    (Wydawnictwa AGH, 2011) Pietroń, Marcin; Wiatr, Kazimierz
    Integracja danych pochodzących z różnych źródeł danych jest bardzo ważnym zagadnieniem w złożonych systemach informatycznych oraz systemach opierających się na sieci globalnej. Rosnąca ilość gromadzonych danych powoduje, że wykonanie operacji integracji danych pochodzących z różnych źródeł dotyczących podobnej dziedziny wiedzy staje się niezbędne. Z tego powodu prowadzone są prace nad opracowaniem algorytmów, aby wykonywały taką operację w sposób automatyczny. Algorytmy te mają dwa główne kryteria jakości. Dokładność mapowania i rozpoznawania pokrewnych elementów oraz złożoność obliczeniową. Publikacja przedstawia prototyp systemu mapowania ontologii (w formacie OWL) opierający się na szacowaniu podobieństwa strukturalnego i lingwistycznego. Podobieństwo to liczone na starcie algorytmu mapowania zmniejsza złożoność algorytmu często zachowując tę samą jakość mapowania. W publikacji zostaną przedstawione rodzaje metryk oraz architektura systemu integracji.
  • Item type:Article, Access status: Open Access ,
    The comparison of parallel sorting algorithms implemented on different hardware platforms
    (Wydawnictwa AGH, 2013) Żurek, Dominik; Pietroń, Marcin; Wielgosz, Maciej; Wiatr, Kazimierz
    Sorting is a common problem in computer science. There are a lot of well-known sorting algorithms created for sequential execution on a single processor. Recently, many-core and multi-core platforms have enabled the creation of wide parallel algorithms. We have standard processors that consist of multiple cores and hardware accelerators, like the GPU. Graphic cards, with their parallel architecture, provide new opportunities to speed up many algorithms. In this paper, we describe the results from the implementation of a few different parallel sorting algorithms on GPU cards and multi-core processors. Then, a hybrid algorithm will be presented, consisting of parts executed on both platforms (a standard CPU and GPU). In recent literature about the implementation of sorting algorithms in the GPU, a fair comparison between many core and multi-core platforms is lacking. In most cases, these describe the resulting time of sorting algorithm executions on the GPU platform and a single CPU core.
  • Item type:Article, Access status: Open Access ,
    FPGA implementation of procedures for video quality assessment
    (Wydawnictwa AGH, 2018) Wielgosz, Maciej; Karwatowski, Michał; Pietroń, Marcin; Wiatr, Kazimierz
    The video resolutions used in a variety of media are constantly rising. While manufacturers struggle to perfect their screens, it is also important to ensure the high quality of the displayed image. Overall quality can be measured using a Mean Opinion Score (MOS). Video quality can be affected by miscellaneous artifacts appearing at every stage of video creation and transmission. In this paper, we present a solution to calculate four distinct video quality metrics that can be applied to a real-time video quality assessment system. Our assessment module is capable of processing 8K resolution in real time set at a level of 30 frames per second. The throughput of 2.19 GB/s surpasses the performance of pure software solutions. The module was created using a high-level language to concentrate on architectural optimization.
  • Item type:Article, Access status: Open Access ,
    Metodyka sprzętowej akceleracji obliczeń w środowisku obliczeniowym komputerów dużej mocy
    (Wydawnictwa AGH, 2007) Pietroń, Marcin; Russek, Paweł; Wiatr, Kazimierz
    In the area of high performance computing hardware acceleration is relatively new method. Undoubtly utilization of custom hardware is well known and widely used in several areas of digital systems. Beside that constant progress in the field of reconfigurable devices and EDA tools enhancement lead to the opportunity to use reconfigurable hardware based acceleration techniques in the area traditionally occupied by general purpose processors. This paper presents some methods used by authors to get higher computation power in scientific computation thanks to custom hardware implemented in programmable devices.