Russek, Paweł
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Item type:Article, Access status: Open Access , Using standard hardware accelerators to decrease computation times in scientific applications(Wydawnictwa AGH, 2009) Kuna, Dawid; Jamro, Ernest; Russek, Paweł; Wiatr, KazimierzNowadays, general-purpose processors are being used in scientific computing. However, when high computational throughput is needed, it's worth to think it over if dedicated hardware solutions would be more efficient, either in terms of performance (or performance to price ratio), or in terms of power efficiency, or both. This paper describes them briefly and compares to contemporary general-purpose processors' architecture.Item type:Article, Access status: Open Access , Sprzętowa implementacja części wielomianowej funkcji orbitalnej na potrzeby obliczeń kwantowo-chemicznych(Wydawnictwa AGH, 2010) Wielgosz, Maciej; Jamro, Ernest; Russek, Paweł; Wiatr, KazimierzThe hardware acceleration module for generating the polynomial part of the orbital function in quantum chemistry calculation is presented. Both implementation and acceleration results are provided in the paper along with the comparison tests (against Itanium 2 processor). The implementation described can be regarded as a milestone on the way towards introducing an efficient hardware implementation of the exchange-correlation potential. The FPGA-based SGI RASC accelerator was used to offload a processor in the most exhausting computations of the SCF routine. The paper also covers issues regarding an integration of the PP (polynomial part) module with the rest of the computational system.Item type:Article, Access status: Open Access , Prototyp systemu profilowania pętli kodu źródłowego jako narzędzia analizy kodu w celu efektywnego przyspieszenia obliczeń wielkiej skali(Wydawnictwa AGH, 2010) Pietroń, Marcin; Russek, Paweł; Wiatr, KazimierzThis paper presents the research on FPGA based acceleration of HPC applications. The most important step to achieve this goal is to extract code that can be sped up. A major drawback is the lack of a tool which could do it. The HPC applications usually consist of a huge amount of complex source code. This is one of the reasons why the process of acceleration should be as automated as possible. Another reason is to make use of HLL (High Level Languages) such as Mitrion-C and Impulse-C. Loop profiling is one of the steps to check if the insertion of HLL to existing HPC source code is possible to gain acceleration of these applications. Hence the most important step to achieve acceleration is to extract the most time consuming code and data dependency, which makes the code easier to be pipelined and parallelized. Data dependency also gives information on how to implement algorithms in an FPGA circuit with the minimal initialization of it during the execution of algorithms.Item type:Article, Access status: Open Access , Softprocesor wizyjny z rekonfigurowalną listą instrukcji(Wydawnictwa AGH, 2006) Kwiatkowski, Marek; Kołton, Mariusz; Russek, Paweł; Wiatr, KazimierzThe Authors present hardware solution implemented in FPGA reconfigurable logic which is a proposal of a universal platform for the image processing. Dedicated hardware is a traditional solution in image processing area as an alternative to the software methods because it offers high processing power/hardware resources ratio. The common disadvantages of that approach is time consuming implementation time. Presented processor with reconfigurable instruction set is a compromise between software and hardware. It offers easier design flow. In the paper discrete cosine transform implementation is presented as an example.Item type:Article, Access status: Open Access , Accelerating SELECT WHERE and SELECT JOIN queries on a GPU(Wydawnictwa AGH, 2013) Pietroń, Marcin; Russek, Paweł; Wiatr, KazimierzThis paper presents implementations of a few selected SQL operations using the CUDA programming framework on the GPU platform. Nowadays, the GPU’s parallel architectures give a high speed-up on certain problems. Therefore, the number of non-graphical problems that can be run and sped-up on the GPU still increases. Especially, there has been a lot of research in data mining on GPUs. In many cases it proves the advantage of offloading processing from the CPU to the GPU. At the beginning of our project we chose the set of SELECT WHERE and SELECT JOIN instructions as the most common operations used in databases. We parallelized these SQL operations using three main mechanisms in CUDA: thread group hierarchy, shared memories, and barrier synchronization. Our results show that the implemented highly parallel SELECT WHERE and SELECT JOIN operations on the GPU platform can be significantly faster than the sequential one in a database system run on the CPU.Item type:Article, Access status: Open Access , Computation acceleration on SGI RASC: FPGA based reconfigurable computing hardware(Wydawnictwa AGH, 2008) Jamro, Ernest; Janiszewski, Marcin; Machaczek, Krzysztof; Russek, Paweł; Wiatr, Kazimierz; Wielgosz, MaciejIn this paper a novel method of computation using FPGA technology is presented. In several cases this method provides a calculations speedup with respcct to the General Purpose Processors (GPP). The main concept of this approach is based on such a design of computing hardware architecture to fit algorithm dataflow and best utilize well known computing techniques as pipelining and parallelism. Configurable hardware is used as a implementation platform for custom designed hardware. Paper will present implementation results of algorithms those are used in such areas as cryptography, data analysis and scientific computation. The other promising areas of new technology utilization will also be mentioned, bioinformatics for instance. Mentioned algorithms were designed, tested and implemented on SGI RASC platform. RASC module is a part of Cyfronet's SGI Altix 4700 SMP system. We will also present RASC modern architecture. In principle it consists of FPGA chips and very fast, 128-bit wide local memory. Design tools avaliable for designers will also be presented.Item type:Article, Access status: Open Access , Perspektywy przyśpieszenia obliczeń w instalacjach o wielkich mocach obliczeniowych za pomocą układów logiki rekonfigurowalnej(Wydawnictwa AGH, 2005) Russek, Paweł; Wiatr, KazimierzThe authors presents already known but not frequently used technique of computation acceleration by circuits of reconfigurable logic with special focus on possibility of its mass usage in multi-processor and multi-threads systems which offer huge computation power. Basic principles and techniques accommodated by reconfigurable computing paradigm are presented and discussion over prospect of this promising technique common usage is preformed taking into account current state of commercially available FPGA reconfigurable logic.Item type:Article, Access status: Open Access , FPGA implementation of exchange-correlation potential calculation for DFT(Wydawnictwa AGH, 2011) Wielgosz, Maciej; Jamro, Ernest; Russek, Paweł; Wiatr, KazimierzW niniejszym artykule przedstawione zostały wyniki implementacji modułu obliczającego potencjał korelacyjno-wymienny dla procedury DFT. Autorzy zaimplementowali wymagające obliczeniowo fragmenty algorytmu DFT, co wiązało się ze znaczną modyfikacją algorytmu, tak by w pełni wykorzystać możliwości struktur rekonfigurowalnych. W konsekwencji powstał zestaw sprzętowych modułów zmiennoprzecinkowych oraz procedur zapewniających komunikacje pomiędzy częścią sprzętową oraz programowaną akceleratora. Przeprowadzone testy na platformie RASC wykazały przyspieszenie obliczeń wynoszące 3x dla modułu obliczającego wartość orbitalu atomowego w punkcie, natomiast większe przyspieszenie uzyskano dla jednostki realizujące obliczenia macierzy S.Item type:Article, Access status: Open Access , Study of OpenCL processing models for FPGA devices(Wydawnictwa AGH, 2019) Szkotak, Piotr; Russek, Paweł; Wiatr, KazimierzIn our study, we present the results of the implementation of the SHA-512 algorithm in FPGAs. The distinguished element of our work is that we conducted the work using OpenCL for FPGA, which is a relatively new development method for reconfigurable logic. We examine loop unrolling as an OpenCL performance optimization method and compare the efficiency of the different kernel implementation types: NDRange, Single-Work Item, and SIMD kernels. In our conclusions, we compare the metrics of the created FPGA accelerator to the corresponding GPGPU solutions. Also, our paper is accompanied by a source code repository to allow the reader to follow and extend our survey.Item type:Article, Access status: Open Access , Metodyka sprzętowej akceleracji obliczeń w środowisku obliczeniowym komputerów dużej mocy(Wydawnictwa AGH, 2007) Pietroń, Marcin; Russek, Paweł; Wiatr, KazimierzIn the area of high performance computing hardware acceleration is relatively new method. Undoubtly utilization of custom hardware is well known and widely used in several areas of digital systems. Beside that constant progress in the field of reconfigurable devices and EDA tools enhancement lead to the opportunity to use reconfigurable hardware based acceleration techniques in the area traditionally occupied by general purpose processors. This paper presents some methods used by authors to get higher computation power in scientific computation thanks to custom hardware implemented in programmable devices.