Browsing by Subject "HPC"

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Access status: Restricted ,
Algorytmy wyboru trasy w środowisku HPC z wykorzystaniem frameworka Xinuk.
(Data obrony: 2020-01-27) Bielech, Maciej
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
Access status: Open Access ,
Evaluating new architectural features of the Intel(r) Xeon(r) 7500 processor for HPC workloads
(Wydawnictwa AGH, 2011) Gepner, Paweł; Fraser, David L.; Kowalik, Michał Filip; Waćkowski, Kazimierz
In this paper we take a look at what the Intel Xeon Processor 7500 family, code named Nehalem-EX, brings to high performance computing. We compare two families of Intel Xeon based systems (Intel Xeon 7500 and Intel Xeon 5600) and present a performance evolution of 16 node clusters based on these CPUs. We compare CPU generations utilizing dual socket platforms and a cluster across a number of HPC benchmarks and focused on different performance field and aspect. We will evaluate also technologies and features like Intels Hyper Threading Technology (HT) and Intel Turbo Boost Technology (Turbo Mode) and the performance implication of these technologies for HPC.
Access status: Open Access ,
FPGA implementation of exchange-correlation potential calculation for DFT
(Wydawnictwa AGH, 2011) Wielgosz, Maciej; Jamro, Ernest; Russek, Paweł; Wiatr, Kazimierz
W niniejszym artykule przedstawione zostały wyniki implementacji modułu obliczającego potencjał korelacyjno-wymienny dla procedury DFT. Autorzy zaimplementowali wymagające obliczeniowo fragmenty algorytmu DFT, co wiązało się ze znaczną modyfikacją algorytmu, tak by w pełni wykorzystać możliwości struktur rekonfigurowalnych. W konsekwencji powstał zestaw sprzętowych modułów zmiennoprzecinkowych oraz procedur zapewniających komunikacje pomiędzy częścią sprzętową oraz programowaną akceleratora. Przeprowadzone testy na platformie RASC wykazały przyspieszenie obliczeń wynoszące 3x dla modułu obliczającego wartość orbitalu atomowego w punkcie, natomiast większe przyspieszenie uzyskano dla jednostki realizujące obliczenia macierzy S.
Access status: Restricted ,
Generowanie map na podstawie rzeczywistych danych do wielkoskalowych symulacji tłumu z wykorzystaniem platformy HPC Xinuk.
(Data obrony: 2020-01-22) Morawiecki, Piotr
Wydział Elektrotechniki, Automatyki, Informatyki i Inżynierii Biomedycznej
Access status: Open Access ,
Heterogeneous GPU&CPU cluster for High Performance Computing in cryptography
(Wydawnictwa AGH, 2012) Marks, Michał; Jantura, Jarosław; Niewiadomska-Szynkiewicz, Ewa; Strzelczyk, Przemysław; Góźdź, Krzysztof
This paper addresses issues associated with distributed computing systems and the application of mixed GPU&CPU technology to data encryption and decryption algorithms. We describe a heterogenous cluster HGCC formed by two types of nodes: Intel processor with NVIDIA graphics processing unit and AMD processor with AMD graphics processing unit (formerly ATI), and a novel software framework that hides the heterogeneity of our cluster and provides tools for solving complex scientific and engineering problems. Finally, we present the results of numerical experiments. The considered case study is concerned with parallel implementations of selected cryptanalysis algorithms. The main goal of the paper is to show the wide applicability of the GPU&CPU technology to large scale computation and data processing.
Access status: Open Access ,
Implementacja w układach FPGA modułu obliczającego funkcję jednoelektronową
(Wydawnictwa AGH, 2009) Wielgosz, Maciej; Jamro, Ernest; Wiatr, Kazimierz
This paper presents an FPGA implementation of a finite sum of the exponential products (orbital function) calculation module. The module is composed of several units. All of them are specially designed, fully pipelined floating-point modules optimized for high speed performance, up to 200 MHz. Execution results revealed speed-up of 5x for the finite sum of the exponential products comparing to Intel Itanium 2 1.6 processor. Orbital function is a computationally critical part of the Hartree-Fock algorithm. Therefore an approach presented here aims to increase the performance of the whole quantum chemistry computational system by extending it with FPGA-based accelerator which is composed of two Xilinx Virtex-4 LX200 chips. It is worth underlining that achieved speed-up is limited by an external memory width constrain. Thus it can be expected that in foreseeable future introduction of next generation of FPGA-based accelerators will allow to increase the speed-up by just porting a project to them without adoption of any changes in the module's architecture.
Access status: Open Access ,
Information extraction from chemical patents
(Wydawnictwa AGH, 2012) Romberg, Mathilde; Klenner, Alexander; Zimmermann, Marc; Bergmann, Sandra
The development of new chemicals or pharmaceuticals is preceded by an indepth analysis of published patents in this field. This information retrieval is a costly and time inefficient step when done by a human reader, yet it is mandatory for potential success of an investment. The goal of the research project UIMA-HPC is to automate and hence speed-up the process of knowledge mining about patents. Multi-threaded analysis engines, developed according to UIMA (Unstructured Information Management Architecture) standards, process texts and images in thousands of documents in parallel. UNICORE (UNiform Interface to COmputing Resources) workflow control structures make it possible to dynamically allocate resources for every given task to gain best cpu-time/realtime ratios in an HPC environment.
Access status: Restricted ,
New serverless API for running tasks on supercomputers
(Data obrony: 2019-10-25) Sosnowski, Damian
Wydział Informatyki, Elektroniki i Telekomunikacji
Access status: Open Access ,
Prototyp systemu profilowania pętli kodu źródłowego jako narzędzia analizy kodu w celu efektywnego przyspieszenia obliczeń wielkiej skali
(Wydawnictwa AGH, 2010) Pietroń, Marcin; Russek, Paweł; Wiatr, Kazimierz
This paper presents the research on FPGA based acceleration of HPC applications. The most important step to achieve this goal is to extract code that can be sped up. A major drawback is the lack of a tool which could do it. The HPC applications usually consist of a huge amount of complex source code. This is one of the reasons why the process of acceleration should be as automated as possible. Another reason is to make use of HLL (High Level Languages) such as Mitrion-C and Impulse-C. Loop profiling is one of the steps to check if the insertion of HLL to existing HPC source code is possible to gain acceleration of these applications. Hence the most important step to achieve acceleration is to extract the most time consuming code and data dependency, which makes the code easier to be pipelined and parallelized. Data dependency also gives information on how to implement algorithms in an FPGA circuit with the minimal initialization of it during the execution of algorithms.
Access status: Open Access ,
Sprzętowa implementacja części wielomianowej funkcji orbitalnej na potrzeby obliczeń kwantowo-chemicznych
(Wydawnictwa AGH, 2010) Wielgosz, Maciej; Jamro, Ernest; Russek, Paweł; Wiatr, Kazimierz
The hardware acceleration module for generating the polynomial part of the orbital function in quantum chemistry calculation is presented. Both implementation and acceleration results are provided in the paper along with the comparison tests (against Itanium 2 processor). The implementation described can be regarded as a milestone on the way towards introducing an efficient hardware implementation of the exchange-correlation potential. The FPGA-based SGI RASC accelerator was used to offload a processor in the most exhausting computations of the SCF routine. The paper also covers issues regarding an integration of the PP (polynomial part) module with the rest of the computational system.