Browsing by Subject "reprogrammable devices"

Now showing 1 - 3 of 3

Access status: Open Access ,
Akcelerator sprzętowy do szyfrowania strumienia danych
(Wydawnictwa AGH, 2008) Kryjak, Tomasz; Gorgoń, Marek
The paper describes a data stream encryption hardware accelerator. The used DES algorithm and its implementation in VHDL language have been discussed. Different FPGA platforms have been evaluated to determine the most suitable one for creating an accelerator cooperating with a PC computer. The software and hardware parts of the presented solution, as well as problems with data transfer form the PC computer to the FPGA device have been described. Correctness and speed of the implemented application have been tested. Finally, the performance of the presented hardware solution and software solutions has been compared.
Access status: Open Access ,
Modelowanie i realizacja algorytmów wideodetekcji na platformie FPGA
(Wydawnictwa AGH, 2006) Gorgoń, Marek; Pawlik, Piotr; Jabłoński, Mirosław; Przybyło, Jaromir
In the present paper the background generation and motion detection algorithms, which are of key importance for the implementation of videodetection, has been presented. A modification of the background generation algorithm, allowing for a proper algorithm functioning at medium and high traffic conditions, has been proposed. An adaptation of the algorithm for implementation in the reprogrammable device has been presented. A modification of the SAD algorithm, used for motion detection has been introduced. The modification allows for unrestricted defining of 32 Regions of Interest of irregular shape and structure in the analyzed image. It gives a capability to conduct the calculation in independent and parallel manner for particular, user-defined, active videodetection regions.
Access status: Open Access ,
Środowisko programowo-sprzętowe do akwizycji, przetwarzania i wizualizacji złożonych sygnałów w oparciu o układy FPGA nowej generacji
(Wydawnictwa AGH, 2006) Gorgoń, Marek
In the present paper digital standards applied for transmission and coding of a visual signal i.e. DVI, HDMI, IEEE1394, USB, Camera Link has been indicated. An increasing of image resolution and frame rate has been discussed for HDTV and DVI-based computer displays. An increase of the computing power necessary for performing image processing in HD vision systems has been noticed. A choosing of computing environment, which can assure necessary computing power, has been considered. Architecture of a system for acquisition, processing and visualization HD images and other complex signals, based on reconfigurable computing platform, cooperating with general-purpose processor has been presented. Particular components being parts of hardware-software stand have been briefly presented.